Hi All, I would like to use this thread to foster technical discussions centered around xbox modchip design. As a first step, I spent sometime last week trying to develop a VHDL implementation for the very simple Aladdin XT modchip using the SST49LF080A LPC flash. It turns out that the LPC specification is very simple and I had a working implementation in just a few hours. I have since tested my implementation using the SST49LF020, SST49LF020A, SST49LF080A on XBOX versions 1.0, 1.1, 1.2, 1.4/1.5. So far, I just have the LPC Memory READ cycle implemented. My ultimate goal is to design with a modchip with a different type of flash device (Parallel NOR or NAND, QSPI, OSPI, HyperFlash, or uSD) as the LPC flash devices seem to be going obsolete. I am more interested in the uSD option because a single uSD card can hold almost all available choices of xbox bioses. There are still a few loose ends to tie like: 1. Driving the d0 pin. Currently, the d0 pin has to be grounded. 2. Incorporate short & long presses of the power button to enable/disable the modchip. 3. Support LPC memory write, LPC IO Read and Write 4. Support Switching memory banks. 5. Include LFRAME support for version 1.6 I know a lot of this has been done by others, but not much is available in terms of actual source code implementation. I am using this as a learning platform for myself, and I hope others can learn from this too. I am releasing the vhdl source code as well as the pin out description for the aladdin xt plus 2 chip. If you have another type of aladdin chip that uses the lc4032v cpld such as the aladdin advance, please test the pin out of your chip and adjust accordingly. The aladdin advance I tested with had the same pin out as the aladdin xt plus 2 except for the D0 and L1 pins. The source as is targets the SST49LF080A flash device but you can easily modify it to fit the LPC chip of your choice. You will need the datasheet handy though. Also, you will need the ispLEVER software from Lattice Semiconductor and a JTAG programmer. The JTAG connections for the aladdin XT plus are discussed in this thread https://assemblergames.com/threads/and-the-aladdin-xt-became-a-decent-modchip.52234/ As a next step, I am looking at a uSD implementation using one of those cheap (~$20) Cyclone IV FPGA boards from aliexpress/ebay. Something like this https://www.arrow.com/en/products/deca/arrow-development-tools from arrow would be great but the $65 price tags seems a bit high to be used as a modchip. I intend to have a SoC running side by side with an LPC implementation of a modchip. This way the design will have the benefit of IO flexibility to support multiple IO peripherals such as a TFT LCD instead of the simple HD4470. With that said, I have a question with regard to how the LPC Memory Read request is done by the MCPX chip on the xbox. According to the book "Hacking the Xbox", the xbox boot rom area spans "0xFF00.0000 to 0xFFFF.FFFF". Any implementation of a modchip will have to adapt/multiplex that memory area to fit the flash chip of choice. This is evident in my design for the SST49LF080A. My question is: Does the LPC Memory Read happen in sequential order (i.e. from 0xFF00.0000 to 0xFFFF.FFFF) or partial sequential or even random? The answer to this question will determine if the cheap (~$20) Cyclone IV FPGA boards + uSD can be easily used to implement a SoC based xbox modchip. Finally, feel free to post your technical questions/answers about xbox modchip design here. My hope is to get some momentum going and help preserve knowledge about xbox modchip design.