It's completely incompatible, the PI bus has a very simple burst system probably used nowhere else for ROM. For that specific NAND you'd need a state machine to: -latch the PI address, then shift it into the NAND. -edge detect a read, write the command for a page read, read until you get to the desired word, and latch the word for PI all before the read cycle is up. PI access doesn't need to be page aligned so this can get tricky, depending on the timing constraints you may have to predict/cache NAND data. You'd need a CPLD no doubt.